1. Field of the Invention
The present invention relates to an electrically rewritable (programmable), non-volatile semiconductor memory device, and more particularly to a method of writing (programming) data in NAND-type flash memories.
2. Description of the Related Art
A NAND-type flash memory comprises a plurality of memory cells serially connected to configure a NAND cell unit such that adjacent cells share a source/drain diffused layer. Therefore, it has a smaller unit cell area and can be provided with mass storage easier than a NOR-type. In addition, it utilizes FN tunneling current for write, which reduces current consumption. Therefore, it is possible to increase the number of memory cells for simultaneous write to achieve substantially high-speed write as an advantage.
In the NAND-type flash memory, a self-boosting scheme is used to boost a NAND cell channel efficiently on writing logical data “1” without varying the threshold. With this scheme, the “1”-write cell (write-inhibited cell) and non-selected cells simultaneously supplied with the write voltage are controlled to cause no electron injection therein. For example, a channel separation voltage 0V is applied to a word line associated with non-selected memory cells located closer to a source line than a selected memory cell supplied with a write voltage Vpgm. In addition, a write non-selection voltage (middle voltage) Vm (Vm<Vpgm) is applied to the remaining non-selected memory cells. As a result, at the time of “1”-data write (that is, non-write), channels in the selected cell and non-selected cells located closer to a bit line than the selected cell, and channels in non-selected cells located closer to the source line than the selected cell are separately boosted.
If the channel separation voltage 0V is applied to a non-selected memory cell right next to the selected cell supplied with the write voltage Vpgm, a band-to-band tunneling current causes a leakage through the drain end of the non-selected cell supplied with 0V, which may cause failed write possibly. Therefore, a non-selected cell supplied with Va (0V<Va<Vm) may be sandwiched between the selected cell supplied with Vpgm and the non-selected cell supplied with the channel separation voltage 0V.
The self-boosting write scheme proposed in the art, however, still leaves the risk of write disturbance (failed write) in non-selected cells. For example, the selection gate transistor on the source line side is turned off with the gate voltage set at 0V for write. In this case, GIDL (Gate Induced Drain Leakage) current flows in the edge of this selection gate transistor, thereby causing failed write in adjacent non-selected cells possibly (see, Lae-Duk Lee et al., “ANEW PROGRAMMING DISTURBANCE IN NAND FLASH MEMORY BY SOURCE/DRAIN HOT-ELECTRONS GENERATED BY GIDL CURRENT”, NVSMW2006, pp. 31-33). The smaller the interval between the selection gate transistor and the memory cell, and the higher the middle voltage Vm applied to non-selected memory cells, the easier this phenomenon arises.